FIG. 21 shows an example of configuration of a signal multiplexing circuit according to the background art (Patent Document 1). FIG. 22 is a time chart showing an example of the operation of the signal multiplexing circuit according to the background art. The abscissa axis in FIG. 22 expresses time. Here is shown the case where a two-channel multiplexed signal is generated.
In FIGS. 21 and 22, an NRZ (Non Return to Zero) signal A0 of channel A input to a signal input terminal 101 is input to a first input terminal of a three-input AND (logical product) 104. An NRZ signal B0 of channel B input to a signal input terminal 102 is input to a first input terminal of a four-input AND 105. A clock CK input to a clock input terminal 103 is successively frequency-divided by TFFs (T flip-flops) 106, 107 and 108 into frequency-divided clocks (CK/2, CK/4 and CK/8) in which the frequency is divided into ½, ¼ and ⅛ in view from the input side. The ⅛ frequency-divided clock output from the TFF 108 is further passed through an inverter 109 from which an inverted ⅛ frequency-divided clock is output. Assuming now that the period of the input clock CK is 2 T, then the pulse period (repetition period) of the NRZ signals A0 and B0 is 16 T.
The three-input AND 104 receives the ¼ frequency-divided clock and the ⅛ frequency-divided clock input to second and third input terminals thereof and outputs an RZ signal A1 obtained by ANDing these clocks and the NRZ signal A0. When the RZ signal A1 shows logic “1”, the RZ signal A1 exhibits a duty ratio of 25% (a “Hi” level period of 4 T and a “Lo” level period of 12 T) for a pulse period of 16 T. On the other hand, the four-input AND 105 receives the ½ frequency-divided clock, the ¼ frequency-divided clock and the inverted ⅛ frequency-divided clock input to second, third and fourth input terminals thereof and outputs an RZ signal B1 obtained by ANDing these clocks and the NRZ signal B0. When the RZ signal B1 shows logic “1”, the RZ signal B1 rises 8 T behind the NRZ signal B0 input to the signal input terminal 102 so that the RZ signal B1 exhibits a duty ratio of 12.5% (a “Hi” level period of 2 T and a “Lo” level period of 14 T) for a pulse period of 16 T.
A selector 110 selects the RZ signals A1 and B1 alternately in accordance with the ⅛ frequency-divided clock and outputs a multiplexed signal D with respective pulse widths of 4 T and 2 T for the pulse period 16 T of the NRZ signals A0 and B0. An OR (logical sum) may be used in place of the selector 110. As the multiplexed signal D, the RZ signals A1 and B1 are multiplexed at duty ratios of 50% and 25% respectively as well as the pulse period of each of channels multiplexed is equally 8 T for the pulse period (repetition period) 16 T of the input signal as one frame.
FIG. 23 shows an example of configuration of a background-art signal separating circuit for separating a two-channel multiplexed signal. Here is shown an example of configuration in which a CDR (Clock Data Recovery) circuit and two latches are used in combination. FIG. 24 is a time chart showing an example of the operation of the CDR circuit. The abscissa axis in FIG. 24 expresses time. FIG. 25 is a time chart showing an example of the operation of the signal separating circuit according to the background art. The abscissa axis in FIG. 25 expresses time.
In FIG. 23, the CDR circuit is composed of a PLL circuit which includes a phase comparator 151, a charge pump circuit 152, a loop filter 153, a VCO (voltage-controlled oscillator) 154, and a ½ frequency divider 155. As shown in FIG. 24, the phase comparator 151 receives a two-channel multiplexed signal D and an output signal CK2 of the ½ frequency divider 155 as two inputs, and outputs a pulse signal s1 having a pulse width corresponding to the phase difference between the two inputs. The pulse signal s1 is integrated by the loop filter 153 via the charge pump circuit 152, so that the oscillation frequency of the VCO 154 is controlled by the integrated output of the loop filter 153.
Although the VCO 154 is set to oscillate approximately twice as high as the pulse frequency of the multiplexed signal D, the oscillation frequency of the VCO 154 is controlled by the function of the CDR circuit (PLL circuit) so as to be accurately equal to twice as high as the pulse frequency of the multiplexed signal D. Incidentally, the CDR circuit performs a synchronous operation in accordance with the logic “1” pulse of the two-channel multiplexed signal D input to the CDR circuit. The time chart shown in FIG. 25 shows a state where the input multiplexed signal D, the output signal CK1 of the VCO 154 and the output signal CK2 of the ½ frequency divider 155 are synchronized with one another.
The output signal CK2 of the ½ frequency divider 155 synchronized with the multiplexed signal D is converted into a clock CK3 further frequency-divided to ½ by a ½ frequency divider 156. The clock CK3 is input to a latch 158. The clock CK3 is converted into an inverted clock CK4 with an inverted phase by an inverter 157. The inverted clock CK4 is input to a latch 159. The latch 158 latches the multiplexed signal D at a leading edge of the clock CK3 and separates a data signal D1 of channel 1. The latch 159 latches the multiplexed signal D at a leading edge of the inverted clock CK4 and separates a data signal D2 of channel 2.
FIG. 26 shows an example of configuration of a background-art signal separating circuit for separating a four-channel multiplexed signal (Patent Document 1). FIG. 27 is a time chart showing an example of the operation of the background-art signal separating circuit shown in FIG. 26. The abscissa axis in FIG. 27 expresses time. Although here is shown a process in which a four-channel multiplexed signal is separated into output terminals corresponding to four channels, a difference in duty ratio (pulse width) between a channel for base timing marker and another channel is used for the separating process. That is, in FIG. 27, four clocks are assigned to the pulse period of each channel, and two clocks (duty ratio of 50%) and one clock (duty ratio of 25%) are assigned to the pulse width of channel A and the pulse width of each of channels B to D, respectively. Incidentally, assume that the clock CK is generated in synchronization with the input four-channel multiplexed signal by use of the CDR circuit shown in FIG. 23.
In FIGS. 26 and 27, a latch 161 latches the input four-channel multiplexed signal D with the clock CK and outputs a latched data string ca. A delay 162 delays the latched data string ca for one clock and outputs a delayed data string cb. A wide pulse detector 163 separates only channel A having a wider pulse width than the other channels by ANDing the latched data string ca and the delayed data string cb and outputs it as a frame leading timing pulse cc. The frame leading timing pulse cc is a key pulse for deciding the physical position of each channel in the latched data string ca, so that channels B to D are separated with this timing used as a base point.
A masking pulse generator 164 receives the latched data string ca and the frame leading timing pulse cc as inputs, and outputs a mask pattern cd obtained by widening the pulse width of the frame leading timing pulse cc by 3 clocks' length corresponding to the leading edge of the following channel B of the data string ca. A phase shifter 165 gives a predetermined delay amount corresponding to the leading edge of each of channels B, C and D in the latched data string ca to the mask pattern cd and outputs a series of mask patterns cd, ce, cf and cg. An channel separator 166 separates data ch, ci, cj and ck of respective channels A to D by ANDing the delayed data string cb with the mask patterns cd, ce, cf and cg.
Incidentally, since channel A must be always a signal of logic “1” to generate the frame leading timing pulse cc and need be different in pulse width from data of the other channels B to D, the channels allowed to be actually used for data transmission are channels B to D.    Patent Document 1: Japanese Unexamined Patent Application Publication No. 2005-303820